News from Semiconductor International

Pressure Builds on Gate-First High-k
Problems with the gate-first approach to high-k/metal gate deposition may force IBM to switch to the gate-last approach pioneered by Intel, technologists said at IEDM. GlobalFoundries and other members of the Fishkill Alliance are putting pressure on IBM to reconsider its gate-first approach, which technologists said has problems with yields, threshold voltage stability and mobilities. more » » »  

Nvidia's Chen Calls for Zero Via Defects
Nvidia needs zero defects from its foundry partners, particularly in the vias on its leading-edge graphics processors, said John Chen, vice president of technology and foundry operations at the GPU powerhouse. With 3.2 billion transistors on its 40 nm graphics processor now coming on the market, the 7.2 billion vias have become a source of problems that the industry must learn to deal with, Chen said in a keynote speech at IEDM. more » » »  

Stanford Scientists Present Flexible Retinal Implants at IEDM
Stanford University scientists presented R&D progress on a flexible retinal implant at the 2009 IEDM in Baltimore. When hit by the light, the solar cells inject current patterns corresponding to the projected images into neural tissue, which ultimately arrive at the visual cortex via the optic nerve, which sends signals to the brain.
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TSMC's Burn Lin Touts E-Beam, Slams EUV
In an IEDM presentation, TSMC lithography director Burn Lin made an impassioned plea for more resources devoted to multi-column e-beam lithography. EUV lithography, by comparison, has such a large energy footprint that Lin said it will need a nuclear power plant next to any high-volume fabs running multiple EUV scanners. "The costs of EUV are not acceptable," Lin added. more » » »  

Toshiba Develops Steep Channel Doping for 20 nm CMOS
Toshiba researchers at IEDM described a channel doping scheme that forms three layers on the surface of the channel: epitaxial silicon, carbon-doped silicon and boron-doped silicon.
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IBM Gains Confidence in 22 nm ETSOI
At the IEDM conference in Baltimore, IBM researchers indicated that a fully depleted CMOS on extremely thin SOI wafers may be the way to go at the 22 nm node. The approach allows reduced short channel effects, and supports gate length scaling to 25 nm and beyond. The fully depleted technology involves Soitec, which supplies wafers with a thin silicon layer on top of the buried oxide.more » » »  

Researchers Describe Use of Diblock Copolymer Lithography at IEDM
Researchers from Stanford developed a top-gated field-effect transistor featuring 20 nm contact holes using diblock copolymer lithography. The material can self-assemble into a regular array of holes on the order of 20 nm or smaller in diameter.
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UMC Takes Hybrid Approach to 28 nm High-k
At IEDM, foundry UMC described a hybrid approach to high-k/metal gate deposition that seeks to take advantage of both the gate-first and gate-last approaches for 28 nm transistors. The hybrid scheme compares with a gate-last method supported by rival Taiwan foundry TSMC, and a gate-first approach by GlobalFoundries for the 28 nm generation. more » » »  

IQE, Intel Describe InGaAs on Si Devices With High-k
IQE and Intel presented a joint paper at IEDM on the development of InGaAs on silicon devices with high-k gate dielectrics. IQE's facility in Bethlehem, Pa., produced the blanket InGaAs QWFET epi wafers grown on silicon substrates using molecular beam epitaxy (MBE).
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Silicon May Prevail Despite Power Fears
Speakers at an IEDM short course on scaling challenges said planar devices made in bulk silicon CMOS are likely to continue to be the basic technology platform for the next decade, despite concerns about power consumption. Although III-V and germanium channels offer high mobilities and lower operating voltages, the challenges of cost, manufacturing complexity and finding a workable gate dielectric may prevent adoption. Scott Thompson, organizer of the short course, said one exception may be Intel, which he said is seriously considering a tri-gate transistor for the outer nodes. more » » »  

Technologists Chart Directions in Technologies at Sematech Workshop
The fifth annual Sematech workshop, co-sponsored by Tokyo Electron Ltd. (TEL) and Aixtron AG and held in conjunction with IEDM, featured a complementary set of more than 40 presentations and panel discussions.
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ASMI Hosts Seminar on ALD at IEDM
The ASM International seminar, held on the last day of IEDM, focused on the materials, equipment and process innovations that enable high-k and metal gates in volume manufacturing, including processes using atomic layer deposition (ALD) and plasma-enhanced ALD (PEALD).
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IEDM Confronts Logic Scaling Challenges
IEDM included presentations on new annealing techniques, finFETs, compound semiconductors and random telegraph noise. The conference, with 215 paper presentations, was preceded by a Sunday short course on scaling challenges organized by TSMC's Howard C.H. Wang. more » » »  

Numonyx Presented Phase Change Memory Research Results at IEDM
Numonyx researchers presented their latest findings on phase change memory (PCM). STMicroelectronics and Numonyx were able to fully integrate a 4 Mb PCM macrocell on a 90 nm CMOS platform, and described 45 nm advances as well.
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