Thin SOI Devices Shine at VLSI SymposiumAt the 2009 Symposium on VLSI Technology in Kyoto, Japan, an IBM R&D team described fully depleted CMOS devices created on extremely thin silicon-on-insulator (ETSOI) wafers, aimed at the 22 nm node and beyond. A Hitachi team presented SRAMs fabbed on ultrathin buried oxide SOI. Both avoided ion implantation steps. more » » »
Toshiba Develops High-k/Ge Gate Stack With Strontium Germanide Interlayer
Toshiba developed an ultrathin, equivalent oxide thickness (EOT) scalable high-k/Ge gate stack with strontium germanide (SrGex ) interlayer for the 16 nm node and beyond. more » » »
Toshiba developed an ultrathin, equivalent oxide thickness (EOT) scalable high-k/Ge gate stack with strontium germanide (SrGex ) interlayer for the 16 nm node and beyond. more » » »
NEC's MRAM Uses Vertical Magnetic SpinNEC presented a spintronics MRAM cell at the Symposium on VLSI Technology in Kyoto, Japan. The cell uses a vertical magnetic structure that may be scalable to sizes smaller than today's SRAM cells. more » » »
Alliance Members Tout Oxide EOT AdvanceResearchers from GlobalFoundries and IBM Research went to the 2009 Symposium on VLSI Technology in Kyoto, Japan, to report progress in reducing the effective oxide thickness (EOT) in the gate stacks for both nFET and pFET devices. The team says it has exceeded EOT and other performance targets set for the 22 nm node. more » » »
Graphene May Have Advantages Over Copper for Future IC Interconnects
The Georgia Institute of Technology said the unique properties of graphene make the material attractive for a wide range of potential electronic devices. more » » »
The Georgia Institute of Technology said the unique properties of graphene make the material attractive for a wide range of potential electronic devices. more » » »
NEC, Toshiba Extend Tech Development Agreements With IBM to 28 nm
NEC Electronics and Toshiba have extended technology development agreements with IBM to participate in the development of a 28 nm, high-k/metal gate, low-power chip technology geared for consumer products. more » » »
NEC Electronics and Toshiba have extended technology development agreements with IBM to participate in the development of a 28 nm, high-k/metal gate, low-power chip technology geared for consumer products. more » » »
Novellus Improves Clean Process for Speed Max Gapfill ToolNovellus said it has improved the in situ clean steps for its CVD gapfill platform, reducing particles and contaminants significantly. Dielectric films tend to adhere to the process chamber components during the deposition process, and must be removed on a periodic basis. more » » »
Entrepix Key to Schiltron's PrototypesSchiltron, a startup with a thin-film transistor 3-D memory architecture, said Entrepix, a CMP technology provider, played a key role in creating prototypes. Entrepix partnered with Schiltron to use CMP in two key process steps of the dual-gate design. more » » »
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